This invention relates to a decoder for a delta-modulated code and, more particularly, to the same which decodes the delta-modulated code obtained from delta modulation of an analog signal to convert it into an original analog signal.
The delta modulation coding system is a coding system which utilizes very simple hardware that does not require an A/D converter and is useful for digitization of, for example, audio signals.
FIG. 13 is a circuit configuration showing a conventional delta modulation system. An analog signal is inputted to an input terminal 101 and is passed through a low pass filter 102 designed to cut high frequency components and thus limit the pass bandwidth. An analog signal with limited bandwidth is passed through a coupling capacitor 103 in order to supply its alternating components to a plus input terminal of a comparator 107. A resistance 105 and a variable resistor 106 are included and determine a direct current voltage level of an input signal line 104 and this voltage level is set generally at 1/2 of the power supply voltage Vcc. An output signal from a flip-flop 108 is integrated by a resistance 110 and a capacitor 111 and the integrated signal is supplied to a minus input terminal of the comparator 107 through a signal input line 112. The comparator 107 compares magnitudes of the two inputted signals and outputs a high voltage (high level) at its output terminal when the signal at the plus terminal is larger, or outputs a low voltage (low level) when the signal at the minus terminal is larger respectively. The output of the comparator 107 is supplied to an input of the flip-flop 108. The flip-flop 108 receives the output signal of the comparator 107 in synchronization with a clock signal applied to a clock terminal 109 and outputs nearly the same high level as the input (voltage approximately equal to Vcc) or the same low level (the grounded voltage, usually 0 volt) and holds the condition as it is until arrival of the next clock. The output voltage of the flip-flop 108 and the relatively high resistance 110 configure a dummy constant current source, and thereby the capacitor 111 is charged up.
Now, signal waveforms on two signal lines 104 and 112 of the comparator 107 are shown in FIG. 14. When a signal 200 is applied to the input signal line 104, a signal waveform on the input signal line 112 becomes as shown with numeral 201. At this time, a delta-modulated code train 202 is outputted at the output terminal of the flip-flop 108. This signal is processed in a digital signal processing portion 113.
An output signal of the delta-modulated code of the digital signal processing portion 113 is supplied to a flip-flop 114 to be received in synchronization with a clock signal applied at a clock terminal 115. An output of the flip-flop 114 is integrated by a relatively high resistance 116 and a capacitor 117 to convert it into an analog signal. When the output of the flip-flop 114 is a code train 202, a signal waveform 201 is obtained as shown in FIG. 14. This signal is formed in stairs and is smoothed by an analog low pass filter 119 and then an analog signal is outputted at an output terminal 120.
Now, in the digital signal processing portion 113, the signal is passed through a digital low pass filter and then is decimated (processing of lowering a sampling frequency) and is converted into a normal PCM (Pulse Code Modulation) code and thereafter is subjected to a variety of processing. However, when an inputted signal waveform is outputted as it is in such a case as digital delay, conversion of the signal into PCM code is not necessary.
The delta modulated code obtained in the above delta modulation coding system is a code train of "1" and "0". In order to perform the normal digital signal processing of "1" and "0", the decimation with the digital low pass filter and the conversion of the signal into the usual PCM signal is required. Therefore, there is a problem in which the required circuit configuration becomes complicated and expensive.